Automated Wafer Alignment Verification System from Japan
Machine vision system verifying fiducial marks and alignment features on wafers for photolithography stepper accuracy. Essential for multi-layer IC patterning. HTS 9030.82.00.00 for semiconductor wafer checking instruments.
Duty Rate — Japan → United States
0%
Rate breakdown
9903.05.860%Articles provided for in subdivision (b) of U.S. note 52 to this subchapter
Import Tips
• Include pattern recognition algorithms specific to semiconductor fiducials in technical specs
• Document overlay measurement accuracy (sub-10nm) for classification support
• Ensure documentation excludes general machine vision applications