Semiconductor Wafer Polishing Pad from Japan
Polyurethane polishing pad engineered for chemical mechanical planarization (CMP) of semiconductor wafers to atomic-level surface finish. This consumable part interfaces with polishing platens in wafer processing equipment. 8487.90.00 for non-electrical machinery parts.
Duty Rate — Japan → United States
12.5%
Rate breakdown
9903.05.4912.5%Section 301 (forced labor) — Japan (col1 rate < 12.5 percent): MFN < 12.5% → total duty capped at 12.5%
Import Tips
• Require CMP-specific pad specifications including slurry compatibility and removal rate data
• Confirm no embedded sensors or electrical features
• Common error: classification as general abrasive under Chapter 68