Semiconductor Wafer Polishing Pad from Japan
Polyurethane polishing pad engineered for chemical mechanical planarization (CMP) of semiconductor wafers to atomic-level surface finish. This consumable part interfaces with polishing platens in wafer processing equipment. 8487.90.00 for non-electrical machinery parts.
Duty Rate — Japan → United States
12.5%
Rate breakdown
9903.05.4912.5%Except for products described in headings 9903.05.85–9903.05.92, articles the product of Japan, with an ad valorem (or ad valorem equivalent) rate of duty under column 1 less than 12.5 percent, as provided for in U.S. note 52 to this subchapter
Import Tips
• Require CMP-specific pad specifications including slurry compatibility and removal rate data
• Confirm no embedded sensors or electrical features
• Common error: classification as general abrasive under Chapter 68