Wafer Polishing Machine from Japan
Automated polisher that achieves mirror-finish flatness on semiconductor wafers for subsequent fabrication into components of electric lamps and electronic tubes sealed in glass envelopes. HTS 8475.10.00.00 classification reflects its position in the glass envelope assembly workflow.
Duty Rate — Japan → United States
12.5%
Rate breakdown
9903.05.4912.5%Section 301 (forced labor) — Japan (col1 rate < 12.5 percent): MFN < 12.5% → total duty capped at 12.5%
Import Tips
• Technical specs must demonstrate semiconductor surface prep for glass sealing processes
• Cross-reference chapter statistical notes excluding Chapter 90 testing polishers