Semiconductor Wafer Test Sample from Japan
8-inch silicon wafer with experimental 3nm process node structures for yield analysis and electrical characterization. Imported by chip design fab for process development testing. Classified 9813.00.30 for semiconductor R&D testing.
Duty Rate — Japan → United States
12.5%
Rate breakdown
9903.05.4912.5%Except for products described in headings 9903.05.85–9903.05.92, articles the product of Japan, with an ad valorem (or ad valorem equivalent) rate of duty under column 1 less than 12.5 percent, as provided for in U.S. note 52 to this subchapter
Import Tips
• Include process node specifications and test matrix documentation
• Class 100 cleanroom transport protocols required for entry
• Wafer maps showing test structures prevent production wafer classification