Semiconductor Wafer Test Sample from Japan
8-inch silicon wafer with experimental 3nm process node structures for yield analysis and electrical characterization. Imported by chip design fab for process development testing. Classified 9813.00.30 for semiconductor R&D testing.
Duty Rate — Japan → United States
12.5%
Rate breakdown
9903.05.4912.5%Section 301 (forced labor) — Japan (col1 rate < 12.5 percent): MFN < 12.5% → total duty capped at 12.5%
Import Tips
• Include process node specifications and test matrix documentation
• Class 100 cleanroom transport protocols required for entry
• Wafer maps showing test structures prevent production wafer classification