Semiconductor Wafer Test Sample from Germany
8-inch silicon wafer with experimental 3nm process node structures for yield analysis and electrical characterization. Imported by chip design fab for process development testing. Classified 9813.00.30 for semiconductor R&D testing.
Duty Rate — Germany → United States
10%
Rate breakdown
9903.05.3910%Except for products described in headings 9903.05.85–9903.05.92 and 9903.05.97, articles the product of a member state of the European Union, with an ad valorem (or ad valorem equivalent) rate of duty under column 1 less than 10 percent, as provided for in U.S. note 52 to this subchapter
Import Tips
• Include process node specifications and test matrix documentation
• Class 100 cleanroom transport protocols required for entry
• Wafer maps showing test structures prevent production wafer classification