Semiconductor Wafer Test Sample from Germany
8-inch silicon wafer with experimental 3nm process node structures for yield analysis and electrical characterization. Imported by chip design fab for process development testing. Classified 9813.00.30 for semiconductor R&D testing.
Duty Rate — Germany → United States
10%
Rate breakdown
9903.05.3910%Section 301 (forced labor) — European Union member state (col1 rate < 10 percent): MFN < 10% → total duty capped at 10%
Import Tips
• Include process node specifications and test matrix documentation
• Class 100 cleanroom transport protocols required for entry
• Wafer maps showing test structures prevent production wafer classification