Semiconductor Wafer Test Sample from China
8-inch silicon wafer with experimental 3nm process node structures for yield analysis and electrical characterization. Imported by chip design fab for process development testing. Classified 9813.00.30 for semiconductor R&D testing.
Duty Rate — China → United States
10%
Rate breakdown
9903.03.0110%Except for products described in headings 9903.03.02–9903.03.11, articles the product of any country, as provided for in subdivision (aa) of U.S. note 2 to this subchapter
Import Tips
• Include process node specifications and test matrix documentation
• Class 100 cleanroom transport protocols required for entry
• Wafer maps showing test structures prevent production wafer classification