QuickLogic eFPGA IP Core Chip from Japan
QuickLogic eFPGA provides embeddable FPGA IP blocks with 4.5K to 36K LEs for SoC integration. Qualifies under HTS 8542.31.00.60 as field programmable logic despite IP core format when delivered as configured IC. Enables custom acceleration in customer ASICs.
Duty Rate — Japan → United States
0%
Rate breakdown
9903.05.860%Articles provided for in subdivision (b) of U.S. note 52 to this subchapter
Import Tips
• IP core FPGAs delivered as ICs need configuration verification proving field programmability
• Distinguish from mask-programmed ASICs via reprogrammability documentation
• Declare target SoC integration specs to prevent semiconductor wafer classification