Electrostatic Wafer Stage from Mexico
Electrostatic stage that grips silicon wafers without physical contact during polishing or grinding in semiconductor equipment under headings 8464-8465. Classified as other work holder in HTS 8466.20.80.65 for principal use in wafer preparation like lapping and polishing. Prevents slip and contamination as noted in statistical definitions.
Duty Rate — Mexico → United States
13.7%
Rate breakdown
9903.03.0110%Except for products described in headings 9903.03.02–9903.03.11, articles the product of any country, as provided for in subdivision (aa) of U.S. note 2 to this subchapter
Import Tips
• Document voltage ratings and cleanroom certification; ensure declaration specifies semiconductor-only use; test for electrostatic discharge compliance with US standards