Electrostatic Wafer Stage from Japan
Electrostatic stage that grips silicon wafers without physical contact during polishing or grinding in semiconductor equipment under headings 8464-8465. Classified as other work holder in HTS 8466.20.80.65 for principal use in wafer preparation like lapping and polishing. Prevents slip and contamination as noted in statistical definitions.
Duty Rate — Japan → United States
12.5%
Rate breakdown
9903.05.4912.5%Section 301 (forced labor) — Japan (col1 rate < 12.5 percent): MFN < 12.5% → total duty capped at 12.5%
Import Tips
• Document voltage ratings and cleanroom certification; ensure declaration specifies semiconductor-only use; test for electrostatic discharge compliance with US standards